`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    18:29:18 04/26/2014 
// Design Name: 
// Module Name:    ClockDivider_2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ClockDivider_2(clk, o_clk,difficulty);
    
input clk;
input [3:0] difficulty;
output reg o_clk;
reg [23:0] count;

  always @ (posedge clk)
  begin
	
	count <= count + 1'b1;
	
	if(difficulty == 2)
	begin
	o_clk = count[17];
	end
	
   else if(difficulty == 3)
	begin
	o_clk = count[16];
	end
	
	else if(difficulty == 4)
	begin
	o_clk = count[15];
	end
	
	else if(difficulty == 5)
	begin
   o_clk = count[14];
	end
	end
endmodule
